AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Download PDF
ID 683657
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

JESD204B IP Core and ADC Configurations

The JESD204B IP Core parameters (L, M, and F) in this hardware checkout are natively supported by the AD9208 device's quick configuration register at address 0x570. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9208 operating conditions

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Global setting for all configuration:
  • N’ = 16
  • CS = 0
  • CF = 0
  • Subclass = 1
  • FPGA Management Clock (MHz) = 100
  • Character Replacement = Enabled
  • PCS Option = Soft PCS
Table 6.  Parameter Configuration
LMF HD S N ADC Sampling Clock (MHz) FPGA Device Clock (MHz) 3 FPGA Link Clock (MHz) 4 FPGA Frame Clock (MHz) 4 Lane Rate (Gbps) DDC enabled Decimation factor Data Pattern
112 0 1 14 800 400 400 400 16 No 1 PRBS-9 Ramp
114 0 2 14 800 400 400 400 16 No 1 PRBS-9 Ramp
211 1 1 14 1600 400 400 400 16 No 1 PRBS-9 Ramp
212 0 2 14 1600 400 400 400 16 No 1 PRBS-9 Ramp
411 1 2 14 3000 375 375 375 15 No 1 PRBS-9 Ramp
412 0 4 14 3000 375 375 375 15 No 1 PRBS-9 Ramp
811 1 4 14 3000 187.5 187.5 187.5 7.5 No 1 PRBS-9 Ramp
812 0 8 14 3000 187.5 187.5 187.5 7.5 No 1 PRBS-9 Ramp
124 0 1 14 400 400 400 400 16 No 1 PRBS-9 Ramp
128 0 2 14 400 400 400 200 16 No 1 PRBS-9 Ramp
222 0 1 14 800 400 400 400 16 No 1 PRBS-9 Ramp
224 0 2 14 800 400 400 400 16 No 1 PRBS-9 Ramp
421 1 1 14 1600 400 400 400 16 No 1 PRBS-9 Ramp
422 0 2 14 1600 400 400 400 16 No 1 PRBS-9 Ramp
821 1 2 14 3000 375 375 375 15 No 1 PRBS-9 Ramp
822 0 4 14 3000 375 375 375 15 No 1 PRBS-9 Ramp
148 0 1 16 400 400 400 200 16 Yes 2 PRBS-9 Ramp
244 0 1 16 800 400 400 400 16 Yes 2 PRBS-9 Ramp
248 0 2 16 800 400 400 200 16 Yes 2 PRBS-9 Ramp
442 0 1 16 1600 400 400 400 16 Yes 2 PRBS-9 Ramp
444 0 2 16 1600 400 400 400 16 Yes 2 PRBS-9 Ramp
841 1 1 16 3000 375 375 375 15 Yes 2 PRBS-9 Ramp
842 0 2 16 3000 375 375 375 15 Yes 2 PRBS-9 Ramp
288 0 1 16 400 400 400 200 16 Yes 2 PRBS-9 Ramp
484 0 1 16 800 400 400 400 16 Yes 2 PRBS-9 Ramp
488 0 2 16 800 400 400 200 16 Yes 2 PRBS-9 Ramp
882 0 1 16 1600 400 400 400 16 Yes 2 PRBS-9 Ramp
884 0 2 16 1600 400 400 400 16 Yes 2 PRBS-9 Ramp
3 The device clock is used to clock the transceiver.
4 The frame clock and link clock is derived from the device clock using an internal PLL.
Level Two Title