Intel® Agilex™ Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 3/18/2021
Public
Document Table of Contents

1. Signal Integrity (SI) in High-Speed PCB Designs

Many factors impact high-speed, serial interface signal integrity, for example, insertion loss (IL), insertion loss deviation (ILD), return loss (RL), crosstalk, and mode conversion. To mitigate these factors, first determine the loss budget for your targeted protocol. Second, select PCB materials and a stackup design that allow you to stay under your loss budget. Then design your PCB with these materials, and run channel compliance analysis.

The final steps are post-layout model extraction and end-to-end system simulation. Use IBIS-AMI models to conduct full-channel, end-to-end eye diagram simulations with the target BER of your targeted protocol. For more details about IBIS-AMI models, contact My Intel support.

Figure 1. Signal Integrity Flow in High-Speed PCB Designs

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