126.96.36.199. R-Tiles Features and Capabilities 188.8.131.52. R-Tile Design Layout Examples 184.108.40.206. Landing Pad Cut-out Optimization of AC Coupling Capacitor 220.127.116.11. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 18.104.22.168. AC Coupling Capacitor Placement Around MCIO Connector 22.214.171.124. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
126.96.36.199. AC Coupling Capacitor Placement Around MCIO Connector
Intel recommends staggered placement for AC coupling capacitors for ease of routing and crosstalk control. Ensure the top layer microstrip trace length from AC coupling capacitor to MCIO connector pin is as short as practical per DFM requirements. Optimize the open field PCB layout to improve the NEXT and FEXT.
Figure 36. AC Coupling Capacitor Staggered Placement Around the MCIO ConnectorThis example shows the crosstalk simulation results based on the Intel Agilex F-Series FPGA Development Board. Red represents TX on layer7, yellow represents RX on layer5, blue represents GND.
Figure 37. Simulation ResultsThe figures show two TX pairs and one RX pair. The simulation includes an AC coupling capacitor, via, part of the microstrip trace and part of the strip-line trace. The simulation results show the NEXT is less than -60.0dB up to 16.0 GHz; the FEXT is less than -50.0dB up to 16.0 GHz.
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