Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

Download PDF
ID 683864
Date 6/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines

Intel implements the following guidelines from the PCIe CEM 5.0 specification version 0.7 in the PCIe development board. For edge finger design, follow the PCIe CEM 5.0 specification.

Ensure inner layer ground under edge-fingers in the high-speed region comprising pins A12/B12 and beyond. The inner layer ground plane must extend to cover the full length of the edge finger region from the main routing area of the board. The inner layer ground plane must lie at least 0.52 mm (20.5 mil) below the edge finger copper. This requirement applies to both sides of the add-in card, so a symmetric pair of shielding planes is used.

Figure 38. Detail of the Core Shielding Ground Plane beneath the Add-in Card Edge FingersThe figure shows a portion of the N-1 plane for reference

Connect a row of plated vias to the inner layer ground plane along the bottom of the edge fingers in the high-speed region comprising pins A12/B12 and beyond. These vias are known as fingertip south vias. The vias must be plated through holes (PTH). You can share them among ground pads on both surfaces of the add-in card. The upper boundary of the via pad must align with the 3.20 mm dimension. Join ground vias in the “I bar” with surface metal.

Align add-in card ground vias serving the north edge-finger ground conductors with the gap between adjacent edge-fingers, to reduce obstruction to signals routed from non-ground edge fingers. The axes of the north ground vias must be no more than 0.38 mm (15 mil) from the boundary of the edge finger pin field. Connect the edge fingers to the ground via with a length of trace whose width matches or exceeds the via pad diameter to minimize the inductance of the ground connection.

Figure 39. Add-in Card Edge Finger RegionThe figure shows south and north edge ground vias. The figure shows a portion of the N-1 plane (e.g. metal 2) for reference

Implement a lateral ground bar to join all the fingertip south vias on the first inner layer (N-1) on each side of the board (Metal 2, for example). The ground bar must align with the north edge of the vias with a distance of 3.20 mm. The ground bar should be 0.71 mm wide, to ensure adequate clearance from the chamfer region.

Figure 40. Detail of the N-1 Layer Geometry Highlighting the Lateral South Ground Bar

Ensure the edge-fingers that are not assigned to ground in the region A12/B12 and beyond are 3.00 mm long and 0.60 mm wide (±0.038mm) (refer to Add-in-Card Edge Fingers Indicating Edge Finger Length). Ensure the upper of the edge-finger is 5.60 mm above the south edge of the add-in card (refer to Add-in-Card Edge Fingers Indicating Edge Finger Length). Small amounts of residual surface metal are permitted in the region extending 0.13 mm beyond the lower end of the edge finger.

Figure 41. Add-in-Card Edge Fingers Indicating Edge Finger LengthThe figure shows a portion of the N-1 plane for reference

Ensure the trace length from the top of an auxiliary signal, or unused edge-finger, to the DC blocking capacitor in the termination circuit is as short as practicable. PCI CEM 5.0 specifies no maximum trace length. Maintain a 42.5Ω trace impedance for traces between edge fingers and DC blocking capacitors. The ground via for the termination network must lie within 1.0 mm (39.4 mil) of the resistor component pad or through-hole.

Figure 42. Add-in Card with AC Termination on All Auxiliary and Reserved Signal Conductors
Level Two Title