Intel® Agilex™ Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

ID 683864
Date 9/26/2022
Public
Document Table of Contents

1.3.2. Power Layers

For details about designing your power distribution network (PDN), see the AN 910: Intel® Agilex™ Power Distribution Network Design Guidelines.

  • Use 1 or 2 oz. thick copper foil where it is possible to provide a stronger current carrying capability in the same routing space.
  • For high current power rails, like the core power rail which may carry a current of more than 100 A, use multi-layers in parallel.
  • When designing in multiple planes for a single supply, add enough stitching vias for the power planes to provide a low resistance vertical path.
  • Place power layers next to a ground layer to create planar capacitance, which aids high-frequency decoupling, reduces electromagnetic interference (EMI) radiation, and enhances electromagnetic compliance (EMC) robustness. Because planar capacitance is inversely proportional to the dielectric thickness between the power and ground planes, choose thin dielectrics between the power and ground planes to increase the planar capacitance while reducing planar spreading inductance.

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