Intel® Agilex™ Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

ID 683864
Date 9/26/2022
Public
Document Table of Contents

1.4.3.2. Optimizing the Passive Channel

You should optimize the whole channel from FPGA BGA pad to module IC pad. You only need to focus optimizing the channel on the PCB, from FPGA BGA pad to optical connector footprint because the optical module is already optimized according to the vendor protocol specification. Refer to the General PCB Design Guidelines for general recommendations on how to optimize PCB channel. You can start board design with Intel FPGA development kits.Refer to All Development Kits.
Figure 21. Typical CEI-112G-VSR channel
  1. Use 3D EM tools for via structure optimization, including FPGA BGA breakout via and optical connector fan out via.
  2. Include connector 3D model for connector fan out via optimization, connector vendor typically can provide encrypted 3D model for connector and PCB joint simulation.
    Figure 22. Connectors
  3. Include crosstalk effects for all components in the simulation (FPGA BGA vias, traces, connector fan out vias)
  4. After you finish the optimization for each element of the channel, cascade them to build a passive channel (from ball to ball) to get channel performance, typically in S parameter format.
  5. Produce traditional channel performance plots like insertion loss, return loss, crosstalk and mode conversion from the channel S parameter to understand the channel performance.
  6. Further optimize it if you find any defects.

Did you find the information on this page useful?

Characters remaining:

Feedback Message