This design example on the PCIe development board uses the breakout trace width and space of 3.35mil and 4.65mil. The TX routes on layer3 and RX routes on layer16 because of the pin definition of the Mini Cool Edge IO (MCIO) connector (the PCIe channels connect FPGA and MCIO connector). The connector TX pins are located at the side near FPGA. The RX pins are located at the opposite side to the FPGA. The RX traces route underneath the MCIO connector pin cut-out if RX traces route on layer3.
Figure 33. MCIO Connector Fan-out Design Example
Red represents TX on layer3, yellow represents RX on layer16, blue represents GND. Includes two vias per ground pin to reduce the ground parasitic effect. Route the micro-strip trace length on the top and bottom as short as possible.
Figure 34. R-tile Breakout Routing Example in BGA Pin Field AreaDark blue represents TX on layer3 (by micro via, top to layer3), red represents RX on layer16 (by through hole via, top to layer16), blue represents GND.
Figure 35. R-tile Breakout Routing Crosstalk Simulation ResultsThe figures show four TX pairs and four RX pairs. The simulation includes FPGA BGA ball, BGA via, breakout trace, and part of main routing. The simulation results show the near end crosstalk (NEXT) is less than -60.0dB up to 16.0 GHz, the far end crosstalk (FEXT) is less than -50.0dB up to 16.0 GHz.