Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

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ID 683864
Date 6/15/2023
Public
Document Table of Contents
Document Table of Contents x
1. Signal Integrity (SI) in High-Speed PCB Designs
1. Signal Integrity (SI) in High-Speed PCB Designs x
1.1. Supported Protocols 1.2. Channel Insertion Loss (IL) Budget Calculation 1.3. PCB Materials and Stackup Design Guidelines 1.4. PCB Design Guidelines 1.5. Document Revision History for the Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
1.3. PCB Materials and Stackup Design Guidelines x
1.3.1. Mitigating Insertion Loss with Dielectric Material 1.3.2. Power Layers 1.3.3. Reference Planes 1.3.4. Layer Assignment 1.3.5. Impedance 1.3.6. Via Drill Size 1.3.7. Fiber Weave 1.3.8. Reference Stackup
1.4. PCB Design Guidelines x
1.4.1. General PCB Design Guidelines 1.4.2. E-Tile PCB Design Guidelines 1.4.3. F-Tile PCB Design Guidelines 1.4.4. P-Tile PCB Design Guidelines 1.4.5. R-Tile PCB Guidelines
1.4.1. General PCB Design Guidelines x
1.4.1.1. PCB Traces 1.4.1.2. PCB Vias 1.4.1.3. Connector Breakout 1.4.1.4. AC Coupling Capacitor 1.4.1.5. Others
1.4.3. F-Tile PCB Design Guidelines x
1.4.3.1. F-Tile Features and Capabilities 1.4.3.2. Optimizing the Passive Channel 1.4.3.3. COM Simulations 1.4.3.4. Simulating the Active Channel
1.4.5. R-Tile PCB Guidelines x
1.4.5.1. R-Tiles Features and Capabilities 1.4.5.2. R-Tile Design Layout Examples 1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor 1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector 1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1. Signal Integrity (SI) in High-Speed PCB Designs

1.4.2. E-Tile PCB Design Guidelines

  • Use a trace impedance of 90-100 Ω for differential signals. The nominal package impedance of the Intel Agilex® 7 FPGA interface is 90 Ω.
  • Route lanes that support 56G PAM4 on shallow layers to reduce via length, with connectors placed on the PCB close to the FPGA to reduce the trace length.
  • Make via stubs as short as possible. Use top-drill, back-drill, buried via, blind via, and micro-via techniques as necessary to shorten the via stubs. Stub lengths of less than 10 mils are recommended.
  • Use layer assignment to keep the coupling length of the closest TX and RX vias as short as possible. A coupling length including via stubs of less than 56 mils is recommended.
  • Use additional ground reference vias for the package edge differential pairs in order to keep ground reference via symmetry for the two signal vias that comprise a differential pair.
Figure 15. Adding Reference Ground Vias for Package Edge Vias
  • Make sure that QSFP-DD connector high-speed signal pin breakouts are on the side that faces toward the FPGA rather than the side that faces the board edge to avoid the long stub caused by the connector pin and PCB pad. For the QSFP-DD connector and PCB pad connection, refer to the following figures.
Figure 16. QSFP-DD Connector and PCB Connection
Figure 17. QSFP-DD Transition Via Layout
  • The zQSFP+ connector has a different connection compared to a QSFP-DD connector as shown in the following figures. Keep the breakouts and the transition vias at the periphery of the zQSFP+ connectors.
Figure 18. zQSFP+ Connector and PCB Connection
Figure 19. zQSFP+ Transition Via Layout
  • Add ground vias on both sides of the connector ground pin and connect them with short, thick ground trace to minimize the inductance of the ground connection. Keep the connector ground pins locally shorted to maintain an equal potential.
Figure 20. zQSFP+ Connector Ground Pin Layout
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