Intel® Agilex™ Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

ID 683864
Date 9/26/2022
Public
Document Table of Contents

1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor

The simulation uses pad size of 0201 capacitor and the PCIe development board stack-up.

The simulation parameters are:

  • Capacitor landing pad size: 12x13 mil rectangle
  • Capacitor interpair pin pitch: 26 mil
  • Signal micro-via drill and pad diameter: 10 mil and 16 mil
  • Signal via depth: top to layer3
Figure 31. Capacitor pad size and the Cut-out Optimization resultsAvoid signals routed underneath the capacitor cut-out. Optimize the cut-out size based on the specific stack-up, the capacitor pad size, and the placement through 3D simulation.

Figure 32. TDR simulation result of 0201 capacitor cut-out

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