Intel® Agilex™ Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

ID 683864
Date 9/26/2022
Document Table of Contents PCB Vias

  • Vias impact high-speed channel loss and the timing budget, so use as few vias as possible for the high-speed differential channel.
  • Keep impedance continuity between the high-speed PCB via and trace. Vias usually have higher capacitance and lower impedance than traces.
  • Optimize via impedance, using a 3D electromagnetic (EM) field solver, by sweeping the anti-pad width, length, and radius for your specific stackup, drill size, and via stub. Keep in mind that:
    • The smaller the drill size, the higher the via impedance
    • The larger the anti-pad size, the higher the via impedance
    • The shorter the via stub, the higher the via impedance
    • The smaller the via top, bottom, and functional pads, the higher the via impedance
Figure 11. Hex Pattern BGA Via Optimization
  • Make sure that each high-speed signal via has a ground via for reference, and make sure that the two signal vias of a differential pair have symmetrical ground vias as the above figure shows. If you do not do this, mode conversion is introduced.
  • Remove non-functional pads for high-speed signal vias and ground vias to lower via capacitance.
  • Make the closest TX and RX signal via coupling length as short as possible through an appropriate layer assignment.
Figure 12. Via Coupling Reduction by Routing Layer Assignment (18L Example)
  • During insertion loss evaluation, a resonance can occur in the frequency range of three times the Nyquist frequency. Control the via stub length to avoid this resonance.

Did you find the information on this page useful?

Characters remaining:

Feedback Message