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1.4.5.1. R-Tiles Features and Capabilities
1.4.5.2. R-Tile Design Layout Examples
1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor
1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area
1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector
1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
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1.4.1.2. PCB Vias
- Vias impact high-speed channel loss and the timing budget, so use as few vias as possible for the high-speed differential channel.
- Keep impedance continuity between the high-speed PCB via and trace. Vias usually have higher capacitance and lower impedance than traces.
- Optimize via impedance, using a 3D electromagnetic (EM) field solver, by sweeping the anti-pad width, length, and radius for your specific stackup, drill size, and via stub. Keep in mind that:
- The smaller the drill size, the higher the via impedance
- The larger the anti-pad size, the higher the via impedance
- The shorter the via stub, the higher the via impedance
- The smaller the via top, bottom, and functional pads, the higher the via impedance
Figure 11. Hex Pattern BGA Via Optimization
- Make sure that each high-speed signal via has a ground via for reference, and make sure that the two signal vias of a differential pair have symmetrical ground vias as the above figure shows. If you do not do this, mode conversion is introduced.
- Remove non-functional pads for high-speed signal vias and ground vias to lower via capacitance.
- Make the closest TX and RX signal via coupling length as short as possible through an appropriate layer assignment.
Figure 12. Via Coupling Reduction by Routing Layer Assignment (18L Example)
- During insertion loss evaluation, a resonance can occur in the frequency range of three times the Nyquist frequency. Control the via stub length to avoid this resonance.