220.127.116.11. R-Tiles Features and Capabilities 18.104.22.168. R-Tile Design Layout Examples 22.214.171.124. Landing Pad Cut-out Optimization of AC Coupling Capacitor 126.96.36.199. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 188.8.131.52. AC Coupling Capacitor Placement Around MCIO Connector 184.108.40.206. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1.4.4. P-Tile PCB Design Guidelines
- For PCIe* add-in-card designs, the insertion loss from the top of the edge finger to the silicon pad (including the package insertion loss and the silicon loss) for both the receiver and transmitter paths must not exceed 8 dB at 8 GHz. Because the P-tile package plus silicon loss is under 3 dB at 8GHZ, you may have an add-in-card PCB loss under 5 dB at 8GHZ.
- Use an insertion loss of 28 dB at 8GHZ including the transmitter and receiver packages as the reference maximum loss for end-to-end channel design, but validate the final design through complete channel simulation and measurements.
- Use a trace impedance of 85 Ω for P-tile differential channels.
- Make via stubs as short as possible. Use top-drill, back-drill, buried via, blind via, and micro-via techniques as necessary to shorten the via stubs. Stub lengths of less than 30 mils are recommended.
- Use additional ground reference vias for the package edge differential pairs in order to keep ground reference via symmetry for the two signal vias that comprise a differential pair.
- Place the AC coupling capacitors on FPGA TX paths close to the FPGA or connector. Do not place them in the middle of the trace routing.
- Optimize the PCIe* slot connector footprint by cutting the ground planes beneath the connector PCB pad, considering the interaction of the connector pin and PCB pad, for less return loss.
- Ensure that the PCIe* slot connector high-speed signal pin breakout is at the periphery of the connector as shown below to avoid a long stub caused by the connector pin and PCB pad.
Figure 24. PCIe* Slot Connector and PCB Pad Connection
Figure 25. PCIe* Slot Connector Breakout
- For an add-in card that supports PCIe* Gen4 16.0 GT/s, make sure that there are no inner-layer conductors of any kind, including ground or power planes, beneath the edge-fingers (for a distance of 15 mils). You may add inner plane layers beneath any of the edge fingers if they extend no more than 2 mm into the edge finger region from the main routing area of the board and are at a depth of at least 15 mils (0.38 mm) beneath the edge finger copper pads on the surface of the PCB.
Figure 26. Add-in Card Edge-finger Regions with Allowed Inner Layer Plane Volume Indicated
- For add-in-card ground fingers, make sure that the distance between a horizontal line across the top edge ground fingers and a horizontal line across the bottom edge of the ground via pads does not exceed 15 mils. Also join the adjacent ground edge-fingers at the lowered via location to provide additional improvement in the ground resonance.
Figure 27. Add-in-card Ground Finger Layout
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