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1.4.5.1. R-Tiles Features and Capabilities
1.4.5.2. R-Tile Design Layout Examples
1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor
1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area
1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector
1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
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1.4.5.2. R-Tile Design Layout Examples
The design examples are from the Intel Agilex® 7 PCIe development board, which has 22 layers and is 2.8mm thick with M7N PCB material.