Intel® Agilex™ Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

ID 683864
Date 9/26/2022
Public
Document Table of Contents

1.3.1. Mitigating Insertion Loss with Dielectric Material

PCB routing from FPGA device to high-speed connectors has very strict IL requirements, for example, high speed Ethernet to the optical module interface and PCI Express* (PCIe) to the gold finger interface.
  • Use the following dielectric constant (Dk) and dissipation factor (Df) values as a reference only for low-loss and ultra-low-loss dielectric materials. Test your design with a vector network analyzer (VNA).
    • Dk =3.5 and Df =0.007 (at 1 GHz) for low-loss material
    • Dk =3.4 and Df =0.002 (at 1 GHz) for ultra-low-loss material
  • Use low-surface-roughness copper materials such as RTF2, VLP, HVLP, and HVLP2 copper to mitigate insertion loss caused by the skin effect. Copper resistance is a function of frequency, as when the frequency increases, the resistive loss increases because of the skin effect. This skin effect reduces the cross-sectional area of the transmission line, which increases the copper resistance.
  • Use thick dielectric material (with the corresponding wider traces) for high-speed differential channel routing layers. Wider traces increase the effective surface area and reduce the sheet resistance.

Did you find the information on this page useful?

Characters remaining:

Feedback Message