188.8.131.52. R-Tiles Features and Capabilities 184.108.40.206. R-Tile Design Layout Examples 220.127.116.11. Landing Pad Cut-out Optimization of AC Coupling Capacitor 18.104.22.168. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 22.214.171.124. AC Coupling Capacitor Placement Around MCIO Connector 126.96.36.199. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1.3.1. Mitigating Insertion Loss with Dielectric Material
PCB routing from FPGA device to high-speed connectors has very strict IL requirements, for example, high speed Ethernet to the optical module interface and PCI Express* (PCIe) to the gold finger interface.
- Use the following dielectric constant (Dk) and dissipation factor (Df) values as a reference only for low-loss and ultra-low-loss dielectric materials. Test your design with a vector network analyzer (VNA).
- Dk =3.5 and Df =0.007 (at 1 GHz) for low-loss material
- Dk =3.4 and Df =0.002 (at 1 GHz) for ultra-low-loss material
- Use low-surface-roughness copper materials such as RTF2, VLP, HVLP, and HVLP2 copper to mitigate insertion loss caused by the skin effect. Copper resistance is a function of frequency, as when the frequency increases, the resistive loss increases because of the skin effect. This skin effect reduces the cross-sectional area of the transmission line, which increases the copper resistance.
- Use thick dielectric material (with the corresponding wider traces) for high-speed differential channel routing layers. Wider traces increase the effective surface area and reduce the sheet resistance.
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