188.8.131.52. R-Tiles Features and Capabilities 184.108.40.206. R-Tile Design Layout Examples 220.127.116.11. Landing Pad Cut-out Optimization of AC Coupling Capacitor 18.104.22.168. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 22.214.171.124. AC Coupling Capacitor Placement Around MCIO Connector 126.96.36.199. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
- Do not route high-speed differential traces under power connectors, power delivery inductors, other interface connectors, crystals, oscillators, clock synthesizers, magnetic devices, or integrated circuits that use or duplicate clocks.
- Keep large spacing (greater than 100 mils) from high-speed traces, vias, and pads to high-noise power nets. High-noise power nets include nets like the switching node (phase node) of a voltage regulator module (VRM), 12 V power net, and high current transient power net.
- If you use a dog-bone fan-out in the BGA pin area, use a ground reference plane cutout under the high-speed signal pad to reduce the capacitance.
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