Intel® Agilex™ Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

ID 683864
Date 9/26/2021
Public
Document Table of Contents

1.4.1.5. Others

  • Do not route high-speed differential traces under power connectors, power delivery inductors, other interface connectors, crystals, oscillators, clock synthesizers, magnetic devices, or integrated circuits that use or duplicate clocks.
  • Keep large spacing (greater than 100 mils) from high-speed traces, vias, and pads to high-noise power nets. High-noise power nets include nets like the switching node (phase node) of a voltage regulator module (VRM), 12 V power net, and high current transient power net.
  • If you use a dog-bone fan-out in the BGA pin area, use a ground reference plane cutout under the high-speed signal pad to reduce the capacitance.

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