188.8.131.52. R-Tiles Features and Capabilities 184.108.40.206. R-Tile Design Layout Examples 220.127.116.11. Landing Pad Cut-out Optimization of AC Coupling Capacitor 18.104.22.168. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 22.214.171.124. AC Coupling Capacitor Placement Around MCIO Connector 126.96.36.199. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
188.8.131.52. Simulating the Active Channel
Passive channel simulation checks most board designs. However, Intel suggests performing active channel simulation (eye diagram simulation with IBIS-AMI model) to further capture the channel behavior with TX and RX devices.
- Contact Intel for the F-tile IBIS-AMI model and user guide.
- Cascade the IBIS-AMI model with the optimized passive channel model in channel simulation tools.
- Tune the TX PMA parameter (auto adaption for RX).
- Run channel simulations to get the optimized eye diagram.
Typically, any non-zero open eye means the channel can work, but you should optimize the TX PMA setting for the best eye opening at the target BER level, to get the best design margin.
Did you find the information on this page useful?