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1.4.5.1. R-Tiles Features and Capabilities
1.4.5.2. R-Tile Design Layout Examples
1.4.5.3. Landing Pad Cut-out Optimization of AC Coupling Capacitor
1.4.5.4. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area
1.4.5.5. AC Coupling Capacitor Placement Around MCIO Connector
1.4.5.6. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
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1.4.3. F-Tile PCB Design Guidelines
For F-tile transceivers, the highest data rate and most challenging protocol is 400G Ethernet application (defined by CEI-112G-VSR/MR/LR or IEEE 802.3ck specification) with a data rate of up to 116G PAM4. This topic focuses on this application. For other applications with lower data rates, refer to the E-tile and P-tile design guidelines.
To design a 400G application interface on a CEI-112G compliant board, the typical design flow is:
- Optimize the passive channel
- COM simulation
- Simulate the active channel