22.214.171.124. R-Tiles Features and Capabilities 126.96.36.199. R-Tile Design Layout Examples 188.8.131.52. Landing Pad Cut-out Optimization of AC Coupling Capacitor 184.108.40.206. R-tile HSSI Breakout Routing in BGA Field Area and MCIO connector Pin Area 220.127.116.11. AC Coupling Capacitor Placement Around MCIO Connector 18.104.22.168. PCIe Gen5 Add-in Card Edge Finger Breakout Design Guidelines
1.4.3. F-Tile PCB Design Guidelines
For F-tile transceivers, the highest data rate and most challenging protocol is 400G Ethernet application (defined by CEI-112G-VSR/MR/LR or IEEE 802.3ck specification) with a data rate of up to 116G PAM4. This topic focuses on this application. For other applications with lower data rates, refer to the E-tile and P-tile design guidelines.
To design a 400G application interface on a CEI-112G compliant board, the typical design flow is:
- Optimize the passive channel
- COM simulation
- Simulate the active channel
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