Intel Agilex® 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines

ID 683864
Date 6/15/2023
Document Table of Contents

1.4.3. F-Tile PCB Design Guidelines

For F-tile transceivers, the highest data rate and most challenging protocol is 400G Ethernet application (defined by CEI-112G-VSR/MR/LR or IEEE 802.3ck specification) with a data rate of up to 116G PAM4. This topic focuses on this application. For other applications with lower data rates, refer to the E-tile and P-tile design guidelines.

To design a 400G application interface on a CEI-112G compliant board, the typical design flow is:

  • Optimize the passive channel
  • COM simulation
  • Simulate the active channel