R-tile devices support 16 channels of SERDES hard IP, running up to 32Gbps NRZ. The PHY supports the channels according to the specification definition of each protocol. R-tile devices support a maximum end-to-end channel loss of 36dB at 16 GHz with BER of 1E-12 for NRZ signaling. This 36dB includes package and silicon losses. For add-in card applications, the maximum insertion loss is 9.5dB at 16 GHz on add-in cards. This loss is from the top of the edge finger to the silicon die pad based on the PCIe CEM5.0 spec. This 9.5dB includes PCB traces, vias, AC caps, and package including the effective die capacitance. Intel recommends running the end-to-end channel passive characteristics simulation, e.g. insertion loss (IL), return loss (RL), and crosstalk simulation, especially if the channel IL is high.
The channel passive characteristics simulation allows for quick risk evaluation at the initial stage of the board and system design. Finally, perform the complete post layout channel timing closure simulation and measurements while considering all impairments, e.g. the crosstalk and manufacturing tolerance.