AN 871: Quick Guide for Intel® Arria® 10 and Intel® Cyclone® 10 GX Transceiver High-Speed Link Tuning

ID 683449
Date 9/26/2018

1. High-Speed Link Tuning Requirements

If high channel loss causes bit error rates (BER) higher than the protocol target BER, you must tune your high-speed links to find optimum equalization values.

To determine if the high BER is due to high channel loss, enable serial loopback with RX VGA setting 0; then check if the high BER persists (serial loopback enables an internal datapath that bypasses the high-speed channel).

Figure 1. Serial Loopback

If the BER is now acceptable, the high BER was caused by high channel loss. In this case, you must perform high-speed link tuning as described in this document. Else, if the BER is still high, the BER was not caused by high channel loss, and you must debug your transceiver PHY (see Optimizing for Crosstalk at High Datarates).

For a high BER that is caused by high channel loss, transceivers offer equalization techniques on both the TX and RX sides in order to compensate for the high channel loss due to PCB traces, high speed connectors, PDN noise, and crosstalk.

To select the optimum equalization values, use the Auto Sweep feature on the Advanced tab of the Transceiver Toolkit to sweep the analog settings.

Find the optimum equalization values through the following steps. These detailed steps use a 10 inch backplane as the baseline.

  1. Enabling and Setting up the Transceiver Toolkit
  2. Sweeping Your Settings
  3. Optimizing Your Settings
  4. Optimizing for Crosstalk at High Datarates