E-Tile Transceiver PHY User Guide

ID 683723
Date 4/01/2024
Document Table of Contents

1. E-Tile Transceiver PHY Overview

The E-tile is a 24-channel, PAM4/NRZ dual-mode transceiver tile that is used in multiple variants of the Stratix® 10 and Agilex™ 7 device families. Refer to the respective Product Tables and Pin-Out Files for Intel® FPGA Devices to find the actual number of transceivers available in each device.

Below is the performance comparison of E-tile to L-tile and H-tile transceiver tiles.

Table 1.  Transceiver Tile Variants
Tile Channel Type Channel Capability Channel Hard IP access
Chip-to-Chip Backplane
L-tile GX 17.4 Gbps (Non-Return-to-Zero (NRZ)) 12.5 Gbps (NRZ) PCIe* Gen3x16
GXT 26.6 Gbps (NRZ)
H-tile GX 17.4 Gbps (NRZ) 17.4 Gbps (NRZ)

PCIe* Gen3x16

100G Ethernet MAC

Firecode Forward Error Correction (FEC)

GXT 28.3 Gbps (NRZ) 28.3 Gbps (NRZ)
E-tile GXE

28.9 Gbps (NRZ),

57.8 Gbps (pulse amplitude modulation (PAM4))

10G/25G/100G Ethernet MAC

Reed Solomon Forward Error Correction (RS-FEC)

The transceiver tiles are connected to the FPGA fabric using Intel® 's Embedded Multi-die Interconnect Bridge (EMIB) technology.