- 18.104.22.168. Switching Between Any Two refclk[0, 1, 2, 3, 4, 5, 6, 7] Reference Clocks or Changing the Reference Clock Frequency on refclk[0, 2, 3, 4, 5, 6, 7, 8]
- 22.214.171.124. Enabling and Disabling Electrical Idle Detector Filtering and Reading Electrical Idle Detector Status
- 10.3.2. Debug Parameters for Intel® Stratix® 10 E-Tile Transceiver Native PHY IP in the Parameter Editor
1. E-Tile Transceiver PHY Overview
The E-tile is a 24-channel, PAM4/NRZ dual-mode transceiver tile that is used in multiple variants of the Intel® Stratix® 10 and Intel® Agilex™ device families. Refer to the respective Product Tables and Pin-Out Files for Intel® FPGA Devices to find the actual number of transceivers available in each device.
Below is the performance comparison of E-tile to L-tile and H-tile transceiver tiles.
|Tile||Channel Type||Channel Capability||Channel Hard IP access|
|L-tile||GX||17.4 Gbps (Non-Return-to-Zero (NRZ))||12.5 Gbps (NRZ)||PCIe* Gen3x16|
|GXT||26.6 Gbps (NRZ)|
|H-tile||GX||17.4 Gbps (NRZ)||17.4 Gbps (NRZ)||
100G Ethernet MAC
Firecode Forward Error Correction (FEC)
|GXT||28.3 Gbps (NRZ)||28.3 Gbps (NRZ)|
28.9 Gbps (NRZ),
57.8 Gbps (pulse amplitude modulation (PAM4))
10G/25G/100G Ethernet MAC
Reed Solomon Forward Error Correction (RS-FEC)
The transceiver tiles are connected to the FPGA fabric using Intel® 's Embedded Multi-die Interconnect Bridge (EMIB) technology.
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