E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

6.5.3.2. Reset Controller Bypass Reset Procedure

In Reset Controller Bypass mode, the reset controller is bypassed and therefore the local TRS and master TRS blocks are not implemented to circulate and stagger the resets.

Because the RS-FEC is enabled, you must complete the TX reset on a specific channel before completely resetting the RX on that channel. Ensure the PMA is ready before asserting or deasserting reset to the individual transceiver digital blocks. Ensure the tx_pma_ready output is asserted before asserting/deasserting the tx_pmaif_reset, tx_rsfec_reset, tx_aib_reset, or rsfec_reset inputs. Ensure that rx_pma_ready output is asserted before asserting or deasserting the rx_pmaif_reset, rx_rsfec_reset, or rx_aib_reset inputs.

Figure 93. RX Reset Timing Waveform
Figure 94. TX Reset Timing Waveform

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