E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

1.2.2. Intel® Stratix® 10 MX H-Tile and E-Tile Configurations

Intel® Stratix® 10 MX devices combine the programmability and flexibility of Intel® Stratix® 10 FPGAs and SoCs with 3D stacked high-bandwidth memory 2 (HBM2). The dynamic random access memory (DRAM) tile is physically connected to the FPGA using Intel® 's Embedded Multi-die Interconnect Bridge (EMIB) technology.

Figure 6.  Intel® Stratix® 10 MX Device with 3 E-Tiles, 1 H-Tile (96 Transceiver Channels) and 2 HBM2

There is no package migration between Intel® Stratix® 10 MX and Intel® Stratix® 10 TX device families (H-tile and E-tile) or Intel® Stratix® 10 GX/SX device families.

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