22.214.171.124. RX Clock Options
|Selected rx_clkout clock source||Full-rate, half-rate, div66||Specifies the clock source for the rx_clkout output clock.
|Enable rx_clkout2 port||On/Off||Enables the optional rx_clkout2 output clock enabling the rx_clkout2 port.|
|Selected rx_clkout2 clock source||Full-rate, half-rate, div66||Specifies the clock source for the rx_clkout2 output clock.
|Selected rx_coreclkin clock network||
|Specifies the type of clock network to route the clock signal to the rx_coreclkin port. Dedicated Clock allows a higher maximum frequency (fmax) between the FPGA core and the transceiver. The number of dedicated clock lines are limited. Intel recommends using dedicated clocks.|
The rx_clkout and rx_clkout2 clocks are asynchronous (no phase relationship) to each other and to any other clock output from the Native PHY IP. You need to take the required precautions to do any data transfers between the two clocks.
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