E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.2.4.3. RX Clock Options

Table 21.  RX Clock Options
Parameter Range Description
Selected rx_clkout clock source Full-rate, half-rate, div66 Specifies the clock source for the rx_clkout output clock.
  • Full-rate: (data rate / PMA width)
  • Half-rate: (data rate / 2*PMA width)
  • Div66: (data rate / 66)
Enable rx_clkout2 port On/Off Enables the optional rx_clkout2 output clock enabling the rx_clkout2 port.
Selected rx_clkout2 clock source Full-rate, half-rate, div66 Specifies the clock source for the rx_clkout2 output clock.
  • Full-rate: (data rate / PMA width)
  • Half-rate: (data rate / 2*PMA width)
  • Div66: (data rate / 66)
Selected rx_coreclkin clock network

Dedicated Clock

Global Clock

Specifies the type of clock network to route the clock signal to the rx_coreclkin port. Dedicated Clock allows a higher maximum frequency (fmax) between the FPGA core and the transceiver. The number of dedicated clock lines are limited. Intel recommends using dedicated clocks.

The rx_clkout and rx_clkout2 clocks are asynchronous (no phase relationship) to each other and to any other clock output from the Native PHY IP. You need to take the required precautions to do any data transfers between the two clocks.

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