E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Document Table of Contents Master-Slave Configuration: Option 2

This configuration is also referred as external EMIB clocking. In this configuration, you can select to import the TX and RX datapath clocks and EMIB clock from a separate transceiver channel. Enable this by selecting the tx_coreclkin2 port and by selecting Enable external clock mode in the Core Interface tab of Native PHY IP Parameter Editor. Once tx_coreclkin2 is enabled, an extra input port is exposed in the core to drive the individual EMIB clock for each 25 Gbps channel. The FEC clock is still provided by the Master channel. This method removes the dependency of a PMA reset between the master and slave channels. The E-tile transceivers can be used in PLL mode to supply a clock in this configuration as shown below. Only transceivers in PLL mode can be used for clocking all four 25G channels. When a transceiver is in PLL mode, you cannot use it for TX or RX operations. Using external EMIB clocking also helps provide a clock to low data rate channels when different data rate channels are placed in same FEC block, for example, 25GE and 24G CPRI. The following figure shows the transceiver in PLL mode providing the datapath clock to four 25 Gbps channels.

In this external EMIB clocking configuration, you must read the pll_locked output from the PLL channel before resetting the transceiver channel:

  • Wait until pll_locked from the PLL channel is asserted before deasserting the transceiver channel reset after device configuration.
  • If pll_locked from the PLL channel is deasserted at any time, hold the respective transceiver channels in reset until pll_locked is reasserted.

The reference clock for the PLL channel should have the same reference clock source as the reference clock for the Ethernet channel to have 0 PPM.

Figure 70. PMA Direct 25 Gbps x 4 (FEC On) Independent Configuration

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