E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.12. rsfec_lane_rx_stat

Register Name Description Address Addressing Mode
rsfec_lane_rx_stat_0 RS-FEC per lane RX status 0x150 32-bits
rsfec_lane_rx_stat_1 0x154
rsfec_lane_rx_stat_2 0x158
rsfec_lane_rx_stat_3 0x15C
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
6 uncorr_cw Set when a FEC code word was not corrected due to too many errors.

RO

WO

-

0x0
5 corr_cw Set when a FEC code word had one or more errors that were corrected.

RO

WO

-

0x0
4 hi_ser

High symbol error rate.

Set when the number of symbol errors in a window of 8192 consecutive codewords has exceeded 417 with RS528 and 6380 with RS544.

If RSFEC_LANE_CFG.indic_byp = 1, then sync header errors are generated towards the PCS layer for a period of 60ms to 75ms.

RO

WO

-

0x0
3 am_5bad

RX was locked (and aligned if RSFEC_CORE_CFG.frac = none) but 5 consecutive alignment/codeword markers were not valid.

Restarts the synchronization.

RO

WO

-

0x0
2 fec_3bad

RX was locked (and aligned if RSFEC_CORE_CFG.frac = none) but 3 consecutive FEC codewords were not corrected.

Restarts the synchronization.

RO

WO

-

0x0
1 not_locked

RX lane not locked.

Not locked to alignment/codeword markers (100GE/128GFC/25GE) or to FEC codewords (32GFC).

One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.

RO

WO

-

0x0
0 sf

Incoming signal fail (transceiver unable to lock to signal).

One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.

RO

WO

-

0x0

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