E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

3.2. Physical Coding Sublayer (PCS) Architecture

The E-tile PCS is located in the EHIP_LANE block, which includes the following features:

  • 64B/66B encoder/decoder
  • Scrambler/descrambler
  • Block distribution/block synchronization
  • Lane reorder

The PCS features are not available within the Native PHY IP core. Refer to the E-Tile Hard IP for Ethernet Intel® FPGA IP User Guide for details about the EHIP_LANE block.

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