3.2. Physical Coding Sublayer (PCS) Architecture
The E-tile PCS is located in the EHIP_LANE block, which includes the following features:
- 64B/66B encoder/decoder
- Block distribution/block synchronization
- Lane reorder
The PCS features are not available within the Native PHY IP core. Refer to the E-Tile Hard IP for Ethernet Intel® FPGA IP User Guide for details about the EHIP_LANE block.
Did you find the information on this page useful?