E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.20. rsfec_cw_pos_rx

Register Name Description Address Addressing Mode
rsfec_cw_pos_rx_0 RS-FEC codeword bit position on RX 0x1C0 32-bits
rsfec_cw_pos_rx_1 0x1C4
rsfec_cw_pos_rx_2 0x1C8
rsfec_cw_pos_rx_3 0x1CC
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
12:0 num

Bit number of first bit in FEC codeword.

Only intended for debug of deterministic latency.

RO

WO

-

0x0000

Did you find the information on this page useful?

Characters remaining:

Feedback Message