E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

4.3. Clock Network Revision History

Document Version Changes
2021.02.10 Made the following change:
  • Added 32b and 66b details to the "PMA Direct with FEC" and "PMA Direct 25 Gbps x 4 (FEC On)" figures.
2020.07.10 Made the following change:
  • Added the 2.5 V and 3.3 V LVPECL options to the RS1 and RS2 source terminations in the "IO Pad Ring - Transceiver Reference Clock Input Pad" figure.
2020.06.02 Made the following change:
  • Added PMA Direct High Data Rate (FEC Off).
2020.01.31 Made the following change:
  • Clarified some blocks in the Core Clock Network Use Case figures.
2019.10.11 Made the following changes:
  • Added clarifications to Reference Clock Pins and QSF Assignments for Reference Clock Pins.
  • Added the Related Information links for the Intel® Agilex™ device documents.
2019.07.29 Made the following changes:
  • Added Dynamic Reconfiguration of Reference Clock.
  • Changed 402.83 to 402.832031.
2019.02.04 Made the following changes:
  • Added instructions for connecting tx_clkout, tx_coreclkin, rx_clkout, and rx_coreclkin.
  • Clarified Master-Slave Configuration: Option 2.
  • Add recommendations for the QSF Assignments for Reference Clock Pins.
  • Changed the maximum reference clock frequency from 500 to 700 and added related instructions to Reference Clock Pins, and clarified that, although the E-tile transceiver reference clock input pin supports a frequency range of 125 MHz to 700 MHz, the reference clock network supports a maximum frequency of 500 MHz.
  • For 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block, clarified that TX and RX Double Width is enabled.
2018.10.08 Made the following changes:
  • Updated the "Clock Sharing 25G Ethernet + 24G CPRI" figure.
  • Updated the "Clock Sharing 25G Ethernet + 24G CPRI + PMA Direct" figure.
  • Added Use Cases and all subsections.
  • Removed the "Clocking Sharing Across Multiple IPs" section.
  • Added the "E-Tile Channel Placement for a Single 25-Gbps PMA Direct Channel (with FEC) Within a Single FEC Block" figure.
  • Changed the QSF assignment for all parameters in the "QSF Assignments for a Single Reference Clock Pin (refclk[0])" table.
2018.07.18 Made the following changes:
  • Added QSF Assignments for Reference Clock Pins.
  • Added Clocking Sharing Across Multiple IPs.
2018.05.15 Made the following changes:
  • Updated figure "REFCLK LVPECL Pins" so that refclk_in_B only connects to REFCLK_1.
  • Changed REFCLK to "reference clock" except for references to REFCLK[0-8] and refclk pins.
2018.01.31 Initial release.

Did you find the information on this page useful?

Characters remaining:

Feedback Message