E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

4.2.2. Single 10 Gbps PMA Direct Channel (without FEC)

Table 56.  Single 10 Gbps PMA Direct Channel Configuration
Data Rate TX and RX Double Width PMA Interface Core Interface tx_clkout Clock Source
10.3125 Gbps Enabled 20 bits 40 bits Half-Rate

For Core Interface FIFO in Phase Compensation mode, connect half rate tx_clkout (257.8125 MHz) to tx_coreclkin and connect rx_clkout (257.8125 MHz) to rx_coreclkin. If you use any other source for tx_coreclkin/rx_coreclkin, make sure tx_coreclkin and rx_coreclkin have 0 PPM difference with tx_clkout and rx_clkout, respectively. E-Tile FIFOs in this mode are used in REGISTER mode.

Figure 68. PMA Direct 10G x 1

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