E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

1.5.3. Reference Clocks

E-tile transceivers include a reference clock network for clocking flexibility and channel bonding. There are up to nine low-voltage positive/pseudo emitter-coupled logic (LVPECL1) reference clock pins on the tile, which are dynamically selectable through two inputs, refclk_in_A and refclk_in_B, to drive the transmitter/receiver. You can configure the pins as either 2.5-V LVPECL compliant or 3.3-V LVPECL tolerant. Intel recommends that you use the default setting, which includes source termination at 2.5 V and AC coupling caps. The Device Data Sheet provides the electrical characteristics under the E-tile section. Additional important electrical information is available in the Device Family Pin Connection Guidelines.

Table 9.  Key Reference Clock Considerations
Consideration Description
Power The reference clock pins support only the low-voltage positive/pseudo emitter-coupled logic (LVPECL) standard. The pins are internally terminated to 2.5 V by default, but are tolerant to 3.3 V as well. You can disable the termination and place external termination to either 2.5 V or 3.3 V. DC block caps and biasing resistors are fixed internally by default. The only requirement is that you meet the LVPECL specifications. The Device Data Sheet provides additional electrical characteristics under the E-tile section. The Device Family Pin Connection Guidelines also contains additional electrical characteristics .
Sharing The nine reference clocks are shared, and they span across all 24 channels within a given E-tile. You must design the transceiver interface accordingly when you use the same reference clock source across multiple E-tiles. Reference clocks are not shared between transceiver tiles because there are no connections between transceiver tiles.
Inputs

Each of the 24 channels has a refclk_in_A input that receives one of the nine reference clocks, refclk[8:0]. The first, refclk[0], is a low-skew balanced clock, and the other eight are non-skew balanced clocks. Only refclk[0] supports channel bonding, which is used mainly for TX clocking. When an RX channel is adjacent to a TX channel and is running at the same rate, you can share any of the reference clocks between the two channels.

Each of the 24 channels also has a refclk_in_B input that only receives refclk[1].

Rate switching Use refclk[1] for rate switching. Use refclk[1] for rate switching or for different TX/RX reference clock frequencies.

The following figures demonstrate the usage of these nine reference clocks through the two inputs.

Figure 15. Dynamically Selected Reference Clocks
Figure 16. Reference Clock Access

The reference clock network spans across the entire transceiver tile. If the design requires a single reference clock to be supplied to more than one transceiver tile, you must route the reference clock to multiple tiles on the printed circuit board (PCB).

Figure 17. Single Reference Clock Used Across two E-Tiles

All 24 channels have access to all nine reference clock options. This provides:

  • Full flexibility on selecting reference clocks on a per-channel basis
  • Channel bonding enabled using refclk[0]

In full duplex mode, each channel can dynamically select any of the nine reference clocks. If RX and TX channels require different clock frequencies, refclk[1] must be used as one of the two clocks. Different TX and RX refclk is supported in simplex mode only; dual simplex is not supported.

Channel bonding is a common technique used to minimize high speed serial lane-lane transmit skew for multi-lane protocols. Channel bonding is supported under the following conditions:

  • Using refclk[0]
  • NRZ PMA direct mode
  • Data rate limited to:
    • 16-bit (parallel data width): 12.0 Gbps
    • 20-bit (parallel data width): 16.0 Gbps
    • 32-bit (parallel data width): 28.0 Gbps
Note: Bonding is only supported within a tile. Bonding is not supported within a package across different tiles, even if the reference clock is shared.
Figure 18. TX and RX with the Same Reference Clock

This configuration shows refclk[1] being used for TX and RX on both channels, enabling use of the same reference clock.

1 Refer to the Device Data Sheet for the acceptable LVPECL specifications.

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