E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.5. rsfec_core_cfg

Description Address Addressing Mode
RS-FEC core configuration 0x30 32-bits
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
1:0 frac

Main operation mode:

0: None, non-fractured, supporting e.g. 100GE, 128GFC:

One client using all 4 physical lanes.

Register tables indexed by physical lane# only uses entry 0, unless otherwise specified.

1: reserved1

2: reserved2

3: Frac4, fractured, supporting e.g. 25GE, 32GFC:

Four clients, each using 1 physical lane.

RW

RO

-

0x0
7 PAM4_Aggregate

Aggregate mode:

0: 4x25GbE aggregate.

1: 100G PAM4 aggregate.

RO

RO

-

0x0

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