E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

4.1. Reference Clock Pins

There are a maximum of nine LVPECL reference clock pins on every E-tile. Refer to the respective Pin-Out Files for Intel® FPGA Devices to find the actual number of reference clocks available in each device. You can configure the pins as either 2.5-V LVPECL compliant or 3.3-V LVPECL tolerant. You can select between 2.5 V and 3.3 V using the QSF statements defined in QSF Assignments for Reference Clock Pins. There are source terminations (RS1 and RS2, 50 Ω each) and load terminations (RL1 and RL2, 250 Ω each), as well as built-in internal AC coupling for differential reference clock input pairs. AC coupling is always enabled irrespective of internal or external termination. Intel recommends using the default setting, which is internal source termination at 2.5 V. Carefully disable internal source termination only when you need external termination at 3.3 V (or 2.5 V). Source termination RS1/2 are bypassed when enabling external termination. For external termination and related reference clock detailed requirements, refer to the Device Family Pin Connection Guidelines. Refer to Device Data Sheet for more details on supported LVPECL specifications and required reference clock specifications.

The E-tile transceiver reference clock input pin supports a frequency range of 125 MHz to 700 MHz, but the reference clock network supports a maximum frequency of 500 MHz. Whenever you configure a reference clock frequency of greater than 500 MHz, the Divide by 2 block is automatically instantiated along with the IP instantiation.

The hardware supports nine reference clocks pins, but the Native PHY IP core parameter editor provides any five reference clocks for a given design implementation. You select which five based on your board layout.

Figure 65. IO Pad Ring - Transceiver Reference Clock Input Pad

E-tile completes the device configuration successfully provided that a valid reference clock frequency, 125 MHz - 500 MHz (if the refclk Divide by 2 is disabled) or 250 MHz - 700 MHz (if the refclk Divide by 2 is enabled), is available during device configuration, which may or may not be the same as what is configured in the transceiver IP. A difference in the configured refclk in the IP compared to the available refclk on the board can cause unexpected transitions on the E-tile TX output.

Make sure you are okay with this behavior until the refclk frequencies are set correctly followed by the recommended reset and device configuration steps as per PMA Analog Reset. If the unexpected transitions are not acceptable, you can disable the transceiver TX output by writing the attribute code 0x0001 with data 0x0003 after device configuration. The E-tile TX may still give some unexpected transitions between the device configuration phase until the attribute code 0x0001 is written.

After correctly configuring back the on-board reference clock, follow the recommended reset and device configuration steps as per PMA Analog Reset to reset the internal controller. Refer to the Register Map for more details on attribute codes and data. Not having a stable reference clock during device configuration causes the configuration to fail.

Figure 66. REFCLK LVPECL PinsThis diagram illustrates the nine refclk pins and the reference clock network within a given E-tile.

For details on LVPECL standard spec, refer to Device Data Sheet.

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