Visible to Intel only — GUID: sex1515624106385
Ixiasoft
Visible to Intel only — GUID: sex1515624106385
Ixiasoft
7.14.2. Optional Dynamic Reconfiguration Logic
The E-tile Transceiver Native PHY IP cores contain soft logic for debug purposes known as the Optional Reconfiguration Logic. This soft logic provides a set of registers that enable you to determine the state of the Native PHY IP cores.
You can enable the following optional reconfiguration logic options in the transceiver Native PHY IP cores:
- Capability registers
- Control and status registers