E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.1. rsfec_top_clk_cfg

Description Address Addressing Mode
RS-FEC Clock configuration register 0x4 32-bits
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
11:8 fec_lane_ena

Rsfec Clock/Lane Enable

Setting these bits enables the clock/lane for RS-FEC mode. This also enables the RX path to the RS-FEC core for that lane (else 0 the valid/data). One bit per lane [bit0=lane0]. If all lanes are disabled, the fec_clk are turned off. One of these bits MUST be set in order to properly access the registers which are in the fec_clk domain (rsfec_cfgcsr_core_csr).

RW

RO

-

0xF
2:0 rsfec_clk_sel

Clock selection for RS-FEC

Indicates which clock to use for rsfec core clock. In addition one of the fec_lane_ena bits must be set for the clock to propagate.

3'b000 : Select Ehip clock

3'b100 : Select EMIB Adapter TX clock 0

3'b101 : Select EMIB Adapter TX clock 1

3'b110 : Select EMIB Adapter TX clock 2

3'b111 : Select EMIB Adapter TX clock 3

All other inputs are invalid and defaults to Ehip clock

RW

RO

-

0x0

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