E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.12.1. Switching Reference Clocks

You can dynamically switch the input clock source.

You can use the reconfiguration interface on the channel instance to specify which reference clock source drives the transmitter, the receiver, or both. The channel supports clocking up to five different reference clock sources of the nine available clocking sources from the reference clock network.

To perform reference clock switching, it is not mandatory to specify more than one reference clock in the Number of reference clocks inputs per channel parameter in the E-tile Native PHY IP configuration window.

Specifying more than one reference clock in the Number of reference clocks inputs per channel parameter and assigning available reference clocks to physical pins in QSF helps store the logical reference clocks pin mux settings (mapping) to the physical reference clocks pins in PMA registers 0xEC, 0xEE, and 0xEF. You can then perform reference clock switching by reading these registers back and then writing to 0xEC[3:0].

If Number of reference clocks inputs per channel is defined as 1 and there are on-board reference clocks available on more than one of the reference clock physical pins of the E-tile, reference clock switching can be performed, but it is your responsibility to know which physical reference clock has a valid on-board clock connected and then write the appropriate value to 0xEC[3:0] to set the mux setting to select the target physical reference clock's pin.

Reference clock switching should follow the recommendations provided in this section for all of the various reference clocks switching use cases.

The number of exposed refclk ports varies according to the number of reference clocks you specify. Use the reconfiguration interface to look up the mux settings for the different refclk# and write the look up value into the channel. Refer to PMA Avalon® Memory-Mapped Interface Registers for look up values.

Figure 107. Reference Clock Network

The reference clock network uses Reference Clock Mux by default which means that:

  • refclk_in_A is the default reference clock at device configuration.
  • refclk_in_A is the default reference clock after a PMA reset.

The most frequent reference clock dynamic reconfiguration use cases are:

  • Switching between any two refclk[0, 1, 2, 3, 4, 5, 6, 7] reference clocks or changing the reference clock frequency on refclk[0, 2, 3, 4, 5, 6, 7, 8].
  • Switching from refclk[0, 1, 2, 3, 4, 5, 6, 7] to refclk[8].
  • Changing the refclk[1] reference clock frequency.

For correct dynamic reconfiguration on reference clocks, find the procedure applicable to your use case in the sections below. Any change in the input reference clock frequency must follow these procedures and must not directly change the reference clock frequency.37 , 38

Requirements for all procedures:

  • A minimum of two clocks bonded out, and refclk[1] must always be bonded out.
  • At least one clock must be stable at a given time.
  • Switch PMA Mux to a stable clock before switching the reference clock mux.

Refer to PMA Attribute Details for how to write a PMA attribute code.

37 The reference clock frequency range is from 125 MHz to 700 MHz as per the Device Data Sheet.
38 PPM variation by protocols is not considered a frequency change.

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