E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.9. rsfec_lane_tx_stat

Register Name Description Address Addressing Mode
rsfec_lane_tx_stat_0 RS-FEC per lane TX status 0x120 32-bits
rsfec_lane_tx_stat_1 0x124
rsfec_lane_tx_stat_2 0x128
rsfec_lane_tx_stat_3 0x12C
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
3 pace_inv

PCS TX pacing violation.

With RS528 .pace_inv is never set.

With RS544 .pace_inv is set when the layer above presents TX data in more than 33 consecutive cycles.

RO

WO

-

0x0
2 resync

PCS TX alignment/codeword marker resync.

Not valid when RS-FEC_LANE_CFG1.eng_cust_am_en = 1.

RO

WO

-

0x0
1 blk_inv

PCS TX 66b invalid block type.

Not valid when transcoding is bypassed.

RO

WO

-

0x0
0 hdr_inv

PCS TX 66b invalid sync header.

Not valid when transcoding is bypassed.

RO

WO

-

0x0

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