E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.2.4.2. TX Clock Options

Table 20.  TX Clock Options
Parameter Range Description
Selected tx_clkout clock source Full-rate, half-rate, div66 Specifies the clock source for the tx_clkout output clock.
Enable tx_clkout2 port On/Off Enables the optional tx_clkout2 output clock.
Selected tx_clkout2 clock source Full-rate, half-rate, div66 Specifies the clock source for tx_clkout2 output clock after enabling the tx_clkout2 port.
Selected tx_coreclkin clock network

Dedicated Clock

Global Clock

Specifies the type of clock network to route the clock signal to the tx_coreclkin port. Dedicated Clock allows a higher maximum frequency (fmax) between the FPGA core and the transceiver. The number of dedicated clock lines are limited.
Enable tx_coreclkin2 port On/Off Enables the optional tx_coreclkin2 input clock.
Selected tx_coreclkin2 clock network

Dedicated Clock

Global Clock

Specifies the type of clock network to route the clock signal to the tx_coreclkin2 port. Dedicated Clock allows a higher maximum frequency (fmax) between the FPGA core and the transceiver. The number of dedicated clock lines are limited.
Enable external clock mode On/Off Enables or disables the tx_coreclkin2 input clock to drive the transfer clock.

The tx_clkout and tx_clkout2 clocks are asynchronous (no phase relationship) to each other and to any other clock output from the Native PHY IP. You need to take the required precautions to do any data transfers between the two clocks.

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