E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

6.3. Reset Block Architecture

The Native PHY IP core's digital reset controller block interacts with a master and local transceiver reset sequencer. The Master TRS and Local TRS blocks work together to stagger the resets to the transceiver channels for noise mitigation.

Figure 77. Reset Block Diagram with Single Reset Control

The Intel® Quartus® Prime Pro Edition software detects the presence of instantiated transceiver Native PHY IP cores and automatically inserts the TRS. The tx_reset and rx_reset inputs, either generated by you or through the reset controller, are received by the Local TRS. The Local TRS also forwards the request to the master TRS for scheduling. TRSs work together to schedule all the requested RS-FEC/PMAIF resets and provide acknowledgment for each request. Use either the reset controller inside the transceiver PHY or your own reset controller with the transceiver reset in manual mode. However, for the TRS to work correctly, the required timing duration must be followed.

Note: The master and local TRS IP is an inferred block and is not visible in the RTL. You have no control over this block.
Table 60.  Reset Signals Required for E-Tile
Reset Transceiver Reset Category
tx_reset TX EMIB reset EMIB Reset
TX PMAIF reset Transceiver Interface Reset
RS-FEC reset RS-FEC Reset
TX RS-FEC reset General RS-FEC reset and includes the TX and RX datapath
rx_reset RX EMIB reset EMIB Reset
RX PMAIF reset Transceiver Interface Reset
RX RS-FEC reset RS-FEC Reset on RX datapath

The tx_reset and rx_reset signals apply the associated transceiver resets.

You can use the Native PHY's Avalon® memory-mapped interface to do a PMA analog reset or to enable and disable the PMA.

You have the option to use tx_reset and rx_reset as the input controls if you enable independent TX and RX reset, or you can use reset as the input to control both TX and RX if you disable independent TX and RX reset. The diagrams "Reset Block Diagram with Independent TX and RX Reset Control" and "Reset Block Diagram with Single Reset Control" in Automatic Reset Mode show the reset IP in both conditions.

You can use the reset controller in automatic or manual reset mode for PMA direct modes, but you need to use the reset controller bypass when using the RS-FEC block in fractured mode or if you want to reconfigure from RS-FEC On to RS-FEC Off or from RS-FEC Off to RS-FEC On.

Resets signals for the Ethernet Hard IP are not included. See E-tile Hard IP for Ethernet Intel® FPGA IP User Guide for details.

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