E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.22. rsfec_err_inj_tx

Register Name Description Address Addressing Mode
rsfec_err_inj_tx_0 RS-FEC error injection mode 0x1E0 32-bits
rsfec_err_inj_tx_1 0x1E4
rsfec_err_inj_tx_2 0x1E8
rsfec_err_inj_tx_3 0x1EC
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
15:8 pat

TX error injection pattern for each lane.

Value specifies which bits are being toggled on each lane, when that lane is hit. There is an 8b pattern per lane. When a 66b word on a lane is hit, 8 consecutive bits out of these 66 are XOR'ed with the pattern.

One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.

RW

RO

-

0x00
7:0 rate

TX error injection rate for each physical lane.

Data is output towards the PMA 66 bits at a time (not to be confused with 66b PCS symbols). The value specifies the fraction of such 66b words to hit. The unit is 1/256th so a value of, say, 7 causes 7/256th of the 66b words being sent on the lane to be hit.

One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.

RW

RO

-

0x00

Did you find the information on this page useful?

Characters remaining:

Feedback Message