E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.2.9. Dynamic Reconfiguration Parameters

Dynamic reconfiguration is the process of modifying transceiver channels to meet changing requirements during device operation.

You can customize channels by triggering reconfiguration during device operation or after device configuration.

Figure 36. Dynamic Reconfiguration Options
Table 30.  Dynamic Reconfiguration Parameters
Parameter Value Description
Enable dynamic reconfiguration On/Off Enables the dynamic reconfiguration interface.
Share reconfiguration interface On/Off When enabled, the Native PHY presents a single Avalon® memory-mapped interface slave for dynamic reconfiguration of all channels. In this configuration, the upper [n-1:19] address bits of the reconfiguration address bus specify the selected channel, where 'n' is the log base 2 of the number of channels. Address bits [18:0] provide the register offset address within the reconfiguration space of the selected channel.
Enable Native PHY Debug Master Endpoint On/Off When enabled, the Native PHY includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® memory-mapped interface slave. The NPDME accesses the reconfiguration space of the transceiver and performs certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel and may also require that you include a jtag_debug link in the system.
Separate reconfig_waitrequest from the status of Avalon® memory-mapped interface arbitration On/Off When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that you enable the Enable control and status registers feature under Optional Reconfiguration Logic.

The default setting is Off.

Enable capability registers On/Off Enables capability registers, which provide high level information about the transceiver configuration. Refer to the PMA Capability Registers section.
Set user-defined IP identifier 0 Sets a user-defined numeric identifier that can be read from the user_identifer offset when the capability registers are enabled.
Enable control and status registers On/Off Enables soft registers for reading status signals and writing control signals on the PHY interface through the embedded debug. Refer to the PMA/PMA Interface Avalon® Memory-Mapped Interface Registers section.
Configuration file prefix File prefix Specifies the file prefix to use for generated configuration files when enabled. Each variant of the IP should use a unique prefix for configuration files.
Generate SystemVerilog package file On/Off When enabled, The IP generates a SystemVerilog package file named [Configuration file prefix]_reconfig_parameters.sv containing parameters defined with the attribute values needed for reconfiguration.
Generate C header file On/Off When enabled, The IP generates a C header file named [Configuration file prefix]_reconfig_parameters.h containing macros defined with the attribute values needed for reconfiguration.
Generate MIF (Memory Initialize File) On/Off When enabled, the IP generates a Memory Initialization File (MIF) named [Configuration file prefix]_reconfig_parameters.mif. The MIF file contains the attribute values needed for reconfiguration in a data format.
Enable multiple reconfiguration profiles On/Off When enabled, you can use the GUI to store multiple configurations. The IP generates reconfiguration files for all of the stored profiles. The IP also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them.
Enable embedded reconfiguration streamer On/Off Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles.
Generate reduced reconfiguration files On/Off When enabled, the Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles.
Number of reconfiguration profiles 1 - 8 Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Store current configuration to profile On/Off Selects which reconfiguration profile to store when clicking the Store profile button.
rcfg_profile_data0 Profile data Dynamic reconfiguration parameter data for Profile 0.
rcfg_profile_data1 Profile data Dynamic reconfiguration parameter data for Profile 1.
rcfg_profile_data2 Profile data Dynamic reconfiguration parameter data for Profile 2.
rcfg_profile_data3 Profile data Dynamic reconfiguration parameter data for Profile 3.
rcfg_profile_data4 Profile data Dynamic reconfiguration parameter data for Profile 4.
rcfg_profile_data5 Profile data Dynamic reconfiguration parameter data for Profile 5.
rcfg_profile_data6 Profile data Dynamic reconfiguration parameter data for Profile 6.
rcfg_profile_data7 Profile data Dynamic reconfiguration parameter data for Profile 7.

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