E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

1.5.4. Ethernet Hard IP (EHIP)

The Ethernet Hard IP is a hardened core of assorted multi-lane and single-lane Ethernet components.

E-tiles include four instances of the Ethernet Hard IP, which in turn supports up to four multi-lane Ethernet MAC stacks, or 24 channels of single-lane Ethernet channel (MAC/PCS) support.

Each Hard IP instance contains a full-featured multi-lane Ethernet (EHIP_CORE) Media Access Control (MAC) layer, which offers a number of interfacing options from the FPGA fabric. The multi-lane core can be used for 100G Ethernet applications. In addition to the multi-lane MAC stack, the Ethernet Hard IP contains six instances of a single-lane Ethernet channel.

Figure 19. Ethernet Hard IP Overview

Reed Solomon Forward Error Correction (RS-FEC) is configurable for single-lane 10 GbE or 25 GbE interfaces as well as multi-lane 100 GbE.

The E-tile implementation of the Ethernet Hard IP provides the following features and support:

  • 4x hardened MACs per E-tile
  • Each MAC block can be configured as:
    • One 100 GbE interface
    • Six 10 GbE / 25 GbE interfaces
    • Bypassable
  • Supports IEEE 1588-2002 standard/Precision Time Protocol (PTP)
    • When used with the multi-lane 100 GbE core or 1-4 lanes of the 10 GbE or 25 GbE stack, two additional transceiver channels are configured for 1588. The location of these two additional channels is hardened for 1588 configuration. Use the E-Tile Channel Placement Tool to see how the channels are configured to support 1588.

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