|Register Name||Description||Address||Addressing Mode|
|rsfec_err_val_tx_0||RS-FEC per lane error injection status||0x1F0||32-bits|
|15:8||inj1s||Same for bits changed from 0 to 1 on each physical lane.||
Number of bits (modulo 256) that were changed from 1 to 0 on each physical lane.
Cleared when the corresponding RSFEC_ERR_INJ_TX.rate is written with a non-zero value after being all zero, i.e. when a test is initiated. A value read from this register is not reliable while injecting. A value read is reliable when the test is completed, i.e. after the lane's RSFEC_ERR_INJ_TX.rate or RSFEC_ERR_INJ_TX.pat has been cleared.
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.
Did you find the information on this page useful?