E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.23. rsfec_err_val_tx

Register Name Description Address Addressing Mode
rsfec_err_val_tx_0 RS-FEC per lane error injection status 0x1F0 32-bits
rsfec_err_val_tx_1 0x1F4
rsfec_err_val_tx_2 0x1F8
rsfec_err_val_tx_3 0x1FC
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
15:8 inj1s Same for bits changed from 0 to 1 on each physical lane.

RO

WO

-

0x00
7:0 inj0s

Number of bits (modulo 256) that were changed from 1 to 0 on each physical lane.

Cleared when the corresponding RSFEC_ERR_INJ_TX.rate is written with a non-zero value after being all zero, i.e. when a test is initiated. A value read from this register is not reliable while injecting. A value read is reliable when the test is completed, i.e. after the lane's RSFEC_ERR_INJ_TX.rate or RSFEC_ERR_INJ_TX.pat has been cleared.

One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.

RO

WO

-

0x00

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