E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.3. Interacting with the Dynamic Reconfiguration Interface

Each transceiver channel contains a reconfiguration interface shared with the PMA Interface (PMAIF), PMA and Embedded Multi-die Interconnect Bridge (EMIB). Additionally, there are six reconfiguration interfaces per E-tile allowing access to the six RS-FEC blocks.

The reconfiguration interface provides direct access to the programmable space of each channel. Communication with the channel reconfiguration interface requires an Avalon® memory-mapped interface master. Because each channel has its own dedicated Avalon® memory-mapped interface, you can dynamically reconfigure channels either concurrently or sequentially, depending on how the Avalon® memory-mapped interface master is connected to the Avalon® memory-mapped interface reconfiguration.

Figure 98. Reconfiguration Interface in Native PHY IP Cores

A Native PHY IP core instance can specify multiple channels. You can use a dedicated reconfiguration interface for each channel or share a single reconfiguration interface across multiple channels to perform dynamic reconfiguration.

Avalon® memory-mapped interface masters interact with the reconfiguration interface by performing Avalon® memory-mapped interface read and write operations to initiate a dynamic reconfiguration of specific transceiver parameters. The dynamic reconfiguration interfaces are compliant with Avalon® memory-mapped interface specifications.

Figure 99. Reconfiguration Interface Ports with Shared Native PHY Reconfiguration Interface

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