E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.7.2.2. Register 0x40141

Bit 0 pulses high to indicate that MIF streaming is in progress. However, you only have ~400 Avalon® memory-mapped interface clock cycles after writing to register 0x40140 to read bit 0 as high (1 in the below figure) before the MIF streamer asserts the Avalon® memory-mapped interface waitrequest and locks the Avalon® memory-mapped interface bus (2 in the below figure). After it releases the bus, bit 0 becomes 0, and the new profile is loaded (3 in the below figure).

Figure 103. MIF Streaming High Level Diagram Showing Avalon® Memory-Mapped Interface Bus Behavior and Register 0x40141 Status

Refer to Reading from the Dynamic Reconfiguration Interface for details.

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