E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

3.1.2. Receiver PMA

The receiver recovers the clock information from the received serial data, deserializes the high-speed serial data and creates a parallel data stream for either the receiver EHIP_LANE, EHIP_CORE, RS-FEC, or the FPGA core.

The receiver portion of the PMA consists of the receiver buffer, the clock data recovery (CDR) unit, and the deserializer.

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