E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

6.5.3.1. Reset Controller Bypass Ports

You can control the reset signals listed in the following table.

Table 64.  Reset Controller Bypass Ports
Port Input/Output Clock Domain Description
rx_aib_reset Input Asynchronous Resets the RX EMIB datapath
rx_pmaif_reset Input Asynchronous Resets the RX PMA digital logic
rx_rsfec_reset Input Asynchronous Resets the RX RS-FEC datapath
rx_transfer_ready Output Asynchronous Output from the Native PHY IP core indicating the RX EMIB datapath is ready
rx_pma_ready Output Asynchronous Output from the PMA indicating the RX PMA is ready
rx_is_lockedtodata Output Asynchronous Output from the Native PHY indicating RX CDR is locked
rsfec_reset Input Asynchronous Resets all (TX and RX) RS-FEC logic
tx_aib_reset Input Asynchronous Resets the TX EMIB datapath
tx_pmaif_reset Input Asynchronous Resets the TX PMA digital logic
tx_rsfec_reset Input Asynchronous Resets the TX RS-FEC datapath
tx_transfer_ready Output Asynchronous Output from the Native PHY IP core indicating the TX EMIB datapath is ready
tx_PMA_ready Output Asynchronous

Output from the PMA indicating the TX PMA is ready. This must be asserted before asserting or deasserting any TX resets

Figure 92. Reset Controller Bypass Ports

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