E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

7.18. Dynamic Reconfiguration Revision History

Document Version Changes
2021.02.10 Made the following changes:
  • In the "Dynamic Reconfiguration with Native PHY in Automatic Reset Mode" and "Dynamic Reconfiguration with Native PHY in Manual Reset Mode" figures, moved disabling the PMA before asserting reset.
  • Removed the polling 0x8B[0] steps added to PMA Attribute Details 2020.09.18 because the steps were for a corner case in simulation for a specific customer.
2020.09.18 Made the following change:
  • Added polling 0x8B[0] steps to PMA Attribute Details.
2020.07.10 Made the following changes:
  • Clarified the Dynamic Reconfiguration Maximum Data Rate Switch instructions.
  • Updated steps to disable the PMA in Embedded Reconfiguration Streamer.
  • Updated the "Dynamic Reconfiguration with Native PHY in Manual Reset Mode" figure.
  • Updated Switching Reference Clocks.
2019.10.11 Made the following changes:
  • Changed the reference clock frequency range is from 125 MHz to 500 MHz to 125 MHz to 700 MHz.
  • Added more instructions for Changing the Reference Clock Frequency on refclk[0, 2, 3, 4, 5, 6, 7, 8] .
  • Added the Related Information links for the Intel® Agilex™ device documents.
2019.07.29 Made the following changes:
  • Updated the Switching Reference Clocks steps.
  • Added procedures for the correct dynamic reconfiguration on reference clocks.
2019.04.19 Made the following changes:
  • Added Register 0x40140.
  • Added Register 0x40141.
2019.02.04 Made the following changes:
  • Added Loading IP Configuration Settings.
  • Added Loading IP Configuration Settings Process.
  • Added Alternative Method for Setting PMA Attributes.
2018.10.08 Made the following changes:
  • Changed some descriptions in the "Dynamic Reconfiguration" section.
  • Added a feature to the " Intel® Stratix® 10 Dynamic Reconfiguration Feature Support" table.
  • Updated the reconfig_write waveform in the "Writing to the Reconfiguration Interface" figure.
  • Switched the order of Disable PMA internal serial loopback and Enable Initial RX Equalizer steps in the "Dynamic Reconfiguration with Native PHY in Automatic Reset Mode" figure.
  • Changed Step 4 in the "Embedded Reconfiguration Streamer" section.
  • Added step 8f and 9 to Switching Reference Clocks.
  • Added a reference to PMA Analog Reset from Switching Reference Clocks.
2018.07.18 Made the following changes:
  • Added reconfiguring the PMA between NRZ and PAM4 (non high data rate) modes as a feature to the "Dynamic Reconfiguration Feature Support" table.
  • Added Multiple Reconfiguration Profiles.
  • Updated Reconfiguration Files with entirely new information.
  • Added Embedded Reconfiguration Streamer.
  • Updated the steps in the Switching Reference Clocks section.
2018.05.15 Made the following changes:
  • Removed "Configuration Files," "Multiple Dynamic Reconfiguration Profiles," "Changing Analog PMA Settings," "Multiple Dynamic Reconfiguration Profiles," "Embedded Dynamic Reconfiguration Streamer," "PMA Attribute Sequencer," and "Native PHY IP Core or Clocking Resources Guided Reconfiguration Flow" sections.
  • Added RX adaptation to the list of PMA analog features.
  • Removed reconfig_rsfec pending support.
  • Removed "PCS" from all sections.
  • Updated MIF file format in the "Configuration Files" section.
  • Updated the configuration file location in the "Multiple Reconfiguration Profiles" section.
  • Removed the "Register read/write sequencer" block from the "Arbitration" figure and list of programmable registers.
  • Deleted data-rate-non-specific recommendation from the "Recommendations for Dynamic Reconfiguration" section.
  • Replaced the text in the "Steps to Perform Dynamic Reconfiguration" section with "Dynamic Reconfiguration with Reset Controller in Automatic Mode" and "Dynamic Reconfiguration with Reset Controller in Manual Mode (required for fractured RS-FEC mode)."
  • Changed "Direct Reconfiguration Flow" with "PMA Register Read/Write Details."
  • Removed references to the "Steps to Perform Dynamic Reconfiguration" section.
  • Added steps to reset and reconfigure the PMA in the "Switching Reference Clocks" section.
  • Removed reference to the PMA register read/write sequencer for this release pending testing in the "Changing Analog PMA Settings" section.
  • Updated the address, writedata, and readdata bus widths in the "Ports and Parameters" and "NPDME" sections.
2018.01.31 Initial release.

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