E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

2.3. Implementing the Transceiver PHY Layer Revision History

Document Version Changes
2022.09.30 Made the following changes:
  • Added new Parameters section to describe how to enable the low rate PAM4 mode.
  • Added footnote to 80 Bit Data Native PHY IP Double-width TX/RX Ports table when RS-FEC transcoder is bypassed.
2021.11.16 Made the following change:
  • Corrected TX/RX PMA Interface Width to 40 in Parallel Data table in Port information.
2021.10.04 Made the following change:
  • Updated the Gearbox RX bitslip operation description in Gearbox 64/66.
2021.02.10 Made the following changes:
  • Changed the SerDes/Output Driver Enable Mode QSF assignment from hssi_xcvr_set_init_seq_serd_en to set_int_seq_serd_en.
  • Changed rx_pma_elecidle from an input to output port in Port Information.
  • Added how to connect i_rsfec_pld_ready description: It is derived from rx_is_lockedtodata for active lanes and tied off for inactive lanes (it is tied to 1'b1).
2020.07.10 Made the following changes:
  • Added the SerDes/Output Driver Enable Mode section including instructions on how to change the TX tri-state value after power-on.
  • Added detail to the SerDes POR Exit Configuration description.
  • Removed RF_P1 Threshold and RF_P0 Threshold from the Initial Adaptation Parameters table.
  • Updated the descriptions of the fifo ports.
  • Added the rsfec_o ports.
2020.06.02 Made the following changes:
  • Added clock domains for ports.
  • Added information about how a deskew marker is generated.
  • Updated the SerDes/Output Driver Enable Mode simplex support parameter.
  • Noted that the tx_clkout and tx_clkout2 clocks are asynchronous to each other and to any other clock output from the Native PHY IP. You need to take the required precautions to do any data transfers between the two clocks. The same is true between rx_clkout and rx_clkout2 and between pll_clkout and pll_clkout2.
  • Added Latency Measurement Options.
  • Updated the allowed values in the Simplex Support Parameters table.
2020.01.31 Made the following changes:
  • Added Enable de-skew, Preserve Unused Transceiver Channels, SerDes/Output Driver Enable Mode, and SerDes POR Exit Configuration options to General and Datapath Parameters.
  • Added two figures: "Deskew Pulse with Double Width Mode Off (Full-Rate)" and "Deskew Pulse with Double Width Mode On (Half-Rate)."
2019.10.11 Made the following changes:
  • Updated RX Deskew Logic.
  • Added "Bit Mapping for Native PHY TX and RX Datapaths."
  • Added Simplex Mode.
  • Added the Related Information links for the Intel® Agilex™ device documents.
2019.07.29 Made the following changes:
  • Added this clarification to PLL Mode: It is used for external EMIB clocking configurations (see the use case in Four 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block .
  • Added value descriptions for the "RS-FEC 78 Bit Bus" and "80 Bit Data Native PHY Double-Width TX/RX Ports" tables.
  • Added the "E-Tile Native PHY PLL Ports" table.
  • Added the Deskew Logic.
  • Added a link to the “Latency Measurement” section of the E-tile Hard IP User Guide: E-tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs for the latency ports.
2019.04.19 Made the following changes:
  • Updated the "TX PMA Pre-equalization" table to agree with the "TX Equalization Settings for PAM4 and NRZ Signals" table.
  • Added rsfec_signal_ok and i_rsfec_pld_ready ports to the "Port Information" table.
  • Added Gearbox 64/66.
  • Added "Bit Mapping for Native PHY TX and RX Datapaths."
2019.02.04 Made the following changes:
  • Added PMA Adaptation.
  • Changed the maximum TX PMA reference clock frequency from 500 to 700.
  • Changed the maximum RX PMA reference clock frequency from 500 to 700.
2018.10.08 Made the following changes:
  • Changed the description of the design flow in the "Transceiver Design Flow in the Native PHY IP Core" section.
  • Added new parameters and updated parameter values and descriptions in the "General, Datapath Options, and Common PMA Options" table.
  • Added a note to the description of the TX PMA data rate parameter in the "TX PMA Options" table.
  • Added the following sections:
    • Reed Solomon Forward Error Correction (RS-FEC) Parameters
    • Fibre-channel and CPRI Modes
    • 128 GFC Mode
    • 25 GbE FEC Direct Mode
    • Interlaken Mode
  • Changed the description of the Use default TX PMA pre-equalization settings parameter in the "TX PMA Pre-equlization" table.
  • Changed the "PMA Interface Options" figure.
  • Updated the "Native PHY IP Core Parameter Editor" figure.
  • Updated the "General, Datapath, and Common PMA Options" figure.
  • Added the following parameters to the "PMA Interface Options" table:
    • Enable tx_enh_pmaif_fifo_almost_full port
    • Enable tx_enh_pmaif_fifo_almost_empty port
    • Enable tx_enh_pmaif_fifo_overflow port
    • Enable tx_enh_pmaif_fifo_underflow port
    • Enable rx_pmaif_fifo_underflow port
    • Enable rx_enh_pmaif_fifo_overflow port
2018.08.08 Made the following changes:
  • Changed the description of the Transceiver mode parameter in the "General, Datapath, and Common PMA Options" table.
2018.07.18 Made the following changes:
  • Added further description about deskew bits to the PMA Direct high data rate PAM4 mode in the "Parallel Data" table.
  • Removed the "Port Diagram" figure.
2018.05.15 Made the following changes:
  • Added further description of the PMA Direct modes in the "Transceiver Design Flow in the Native PHY IP Core" section.
  • Updated the "Native PHY IP Core Parameter Editor" figure.
  • Added more description to the following parameters in the "Core Interface Parameters" table:
    • Enable TX double width transfer
    • Enable RX double width transfer
  • Added the "Port Information" table.
  • Changed the following parameters in the "General, Datapath Options, and Common PMA Options" table:
    • Removed the Enable RS-FEC parameter
    • Removed the Enable datapath and interface reconfiguration parameter
    • Changed the values and description for the Transceiver mode parameter
  • Added the following parameters to the "TX PMA Options" table:
    • TX PMA clockout post divider
    • TX PMA reference clock frequency
  • Added the following parameters to the "RX PMA Options" table:
    • RX PMA clockout post divider
    • RX PMA reference clock frequency
  • Added the "Reset Parameters" section.
  • Added the "Dynamic Reconfiguration Parameters" section.
  • Added the following ports to the "Port Information" table:
    • reconfig_waitrequest
    • reconfig_readdata
    • reconfig_writedata
    • reconfig_address
    • reconfig_read
    • reconfig_write
    • reconfig_reset
    • reconfig_clk
  • Added the "Parallel Data" table.
2018.01.31 Initial release.

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