E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.6. rsfec_lane_cfg

Register Name Description Address Addressing Mode
rsfec_lane_cfg_0 RS-FEC per lane configuration 0x40 32-bits
rsfec_lane_cfg_1 0x44
rsfec_lane_cfg_2 0x48
rsfec_lane_cfg_3 0x4C
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
3 rs544

Selects the RS encoder/decoder mode:

0: Use RS(528,514).

1: Use RS(544,514).

RW

RO

-

0x0
2 indic_byp

Bypass error indication (to reduce latency):

0: Sync headers in the 66b words extracted from uncorrectable FEC codewords are deliberately invalidated.

1: 66b words extracted from uncorrectable codewords are not explicitly marked bad. When number of symbol errors in a block of 8192 consecutive codewords has exceeded 417 with RS528 and 6380 with RS544, then sync header errors are generated towards the PCS layer for a period of 60ms to 75ms.

RW

RO

-

0x0
1 scr

Set to enable PN-5280 scrambling/descrambling.

Must be set to 1 when RS-FEC_CORE_CFG.frac = frac4 and RS-FEC_LANE_CFG.fc = 1 (i.e. 32GFC), otherwise it must be set to 0.

RW

RO

-

0x0
0 fc Set to enable Fibre Channel mode.

RW

RO

-

0x0

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