6.6. Master-Slave Clocking Option 2 Reset Details
When multiple transceiver channels are configured in master-slave clocking option 2 (an external transceiver channel configured as a PLL generates the clocks used to transfer data across the EMIB), one channel acts as the master channel. Asserting tx_aib_reset or rx_aib_reset ports, visible in manual reset or reset controller bypass modes, on the master channel causes the EMIB transfer clock from the external PLL to not be propagated to the slave channels. This results in both the master and slave channels to stopping the transfer of data across the EMIB. EMIB reset is only required when the clock used to transfer data across the EMIB gets disrupted, which does not occur in master-slave clocking option 2.
Additionally, the master channel cannot be dynamically reconfigured from RS-FEC enabled mode to PMA direct mode.
Dynamic reconfiguration without data rate change
Example: a PMA analog reset while doing link tuning
Dynamic reconfiguration with data rate change
Example: changing from one data rate to another data rate in RS-FEC-direct mode
|Dynamic reconfiguration from RS-FEC enabled to PMA direct|
|Master||Do not assert tx_aib_reset or rx_aib_reset||Do not assert tx_aib_reset or rx_aib_reset||Not supported|
|Slave||Do not assert tx_aib_reset or rx_aib_reset||Do not assert tx_aib_reset or rx_aib_reset||Assert tx_aib_reset and rx_aib_reset|
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