E-Tile Transceiver PHY User Guide

ID 683723
Date 9/30/2022
Public
Document Table of Contents

9.5.18. rsfec_ln_mapping_rx

Register Name Description Address Addressing Mode
rsfec_ln_mapping_rx_0 RS-FEC FEC lane mapping 0x1A0 32-bits
rsfec_ln_mapping_rx_1 0x1A4
rsfec_ln_mapping_rx_2 0x1AB
rsfec_ln_mapping_rx_3 0x1AC
The reset values in this table represents register values after a reset has completed.
Bit Name Description

SW Access

HW Access

Protection

Reset
1:0 fec_lane

FEC lane# received on each physical lane.

Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).

RO

WO

-

0x0

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